Architectures pour des circuits fiables de hautes performances

Les technologies nanométriques ont réduit la fiabilité des circuits électroniques, notamment en les rendant plus sensible aux phénomènes extérieurs. Cela peut provoquer une modification des composants de stockage, ou la perturbation de fonctions logiques. Ce problème est plus préoccupant pour les mémoires, plus sensibles aux perturbations extérieures. Les codes correcteurs d'erreurs constituent l'une des solutions les plus utilisées, mais les contraintes de fiabilité conduisent à utiliser des codes plus complexes, et qui ont une influence négative sur la bande passante du système. Nous proposons une méthode qui supprime la perte de temps due à ces codes lors de l'écriture des données en mémoire, et la limite aux seuls cas où une erreur est détectée lors de la lecture. Pour cela on procède à la décontamination du circuit après qu'une donnée erronée ait été propagée dans le circuit, ce qui nécessite de restaurer certains des états précédents de quelques composants de stockage par l'ajout de FIFO. Un algorithme identifiant leurs lieux d'implémentation a également été créé. Nous avons ensuite évalué l'impact de cette méthode dans le contexte plus large suivant : la restauration d'un état précédent de l'ensemble du circuit en vue de corriger une erreur transistoire susceptible de se produire n'importe où dans le circuit.Nanometric technologies led to a decrease of electronic circuit reliability, especially against external phenomena. Those may change the state of storage components, or interfere with logical components. In fact, this issue is more critical for memories, as they are more sensitive to external radiations. The error correcting codes are one of the most used solutions. However, reliability constraints require codes that are more and more complex. These codes have a negative effect on the system bandwidth. We propose a generic methodology that removes the timing penalty of error correcting codes during memory's write operation. Moreover, it limits the speed penalty for read operation only in the rare case an error is detected. To proceed, the circuit is decontaminated after uncorrected data were propagated inside the circuit. This technique may require restoring some past states of few storage components by adding some FIFO. An algorithm that identifies these components was also created. Then we try to evaluate the impact of such a technique for the following issue: the global state restoration of a circuit to erase all kinds of soft errors, everywhere inside the circuit.SAVOIE-SCD - Bib.électronique (730659901) / SudocGRENOBLE1/INP-Bib.électronique (384210012) / SudocGRENOBLE2/3-Bib.électronique (384219901) / SudocSudocFranceF

JESÚS GARCÍA, REGINA [Material gráfico]

Copia digital. Madrid : Ministerio de Educación, Cultura y Deporte, 201

Evaluating the SEE sensitivity of a 45nm SOI Multi-core Processor due to 14 MeV Neutrons

The aim of this work is to evaluate the SEE sensitivity of a multi-core processor having implemented ECC and parity in their cache memories. Two different application scenarios are studied. The first one configures the multi-core in Asymmetric Multi-Processing mode running a memory-bound application, whereas the second one uses the Symmetric Multi-Processsing mode running a CPU-bound application. The experiments were validated through radiation ground testing performed with 14 MeV neutrons on the Freescale P2041 multi-core manufactured in 45nm SOI technology. A deep analysis of the observed errors in cache memories was carried-out in order to reveal vulnerabilities in the cache protection mechanisms. Critical zones like tag addresses were affected during the experiments. In addition, the results show that the sensitivity strongly depends on the application and the multi-processsing mode used

Simulink-based MPSoC Design: New Approach to Bridge the Gap between Algorithm and Architecture Design

ISBN: 0-7695-2896-1International audienceThe rise of the abstraction level when designing the hardware (HW) and software (SW) parts of multiprocessor systems on chip (MPSoC) permits to master the growing complexity of these systems. However, it generates a huge gap between the concepts of system level specification and those used for implementation and synthesis of HW/SW MPSoC. This paper deals with the system level design for rapid prototyping of MPSoC starting from Matlab/Simulink specification. We propose a new approach to establish a bridge between the system level specification and the HW/SW architecture at the implementation level

An Architecture for an efficient multiprocessor development environment: the fast distributed executive for reactive system

International audienc

Automatic Code Generation for MPSoC Platform Starting From Simulink/Matlab : New Approach to Bridge the Gap between Algorithm and Architecture Design

isbn: 978-1-4244-1751-3International audienceThis paper deals with the system level design flow and methodology for rapid prototyping of multiprocessor systems on chip (MPSoC) starting from Matlab/Simulink specification. The rise of the abstraction level when designing the hardware (HW) and software (SW) parts of MPSoC permits to master the growing complexity of these systems. However, it generates a huge gap between the concepts of system level specification and those used for implementation and synthesis of HW/SW MPSoC. In this paper, we propose a new approach to establish a bridge between the system level specification in Matlab/Simulink and the HW/SW architecture at the implementation level

X-Ray Fault Injection: Reviewing Defensive Approaches from a Security Perspective

International audienceWith the emergence of a novel fault injection technique based on nanofocused X-Ray beams, these attacks have been proven feasible even when using simple laboratory X-Ray sources. X-Rays can induce parametric shifts in MOS components, mostly at the level of oxides: if properly controlled, these shifts lead to reversible stuck-at faults. It is therefore established that X-Rays can indeed be considered a threat that needs to be addressed in the future when designing secure circuits. In this paper, we discuss how countermeasures issued from the state of the art can be exploited to mitigate or resist against this novel attack.</p

GNOCS: an ultra-fast, highly extensible, cycle-accurate GPU-Based parallel Network-on-Chip simulator

International audienceWith the continuous decrease in feature sizes and the recent emergence of 3D stacking, chips comprising thousands of nodes are becoming increasingly relevant, and state-of-the-art NoC simulators are unable to simulate such a high number of nodes in reasonable times. In this demo, we showcase GNoCS, the first detailed, modular and scalable parallel NoC simulator running fully on GPU (Graphics Processing Unit). Based on a unique design specifically tailored for GPU parallelism, GNoCS is able to achieve unprecedented speedups with no loss of accuracy. To enable quick and easy validation of novel ideas, the programming model was designed with high extensibility in mind. Currently, GNoCS accurately models a VC-based microarchitecture. It supports 2D and 3D mesh topologies with full or partial vertical connections. A variety of routing algorithms and synthetic traffic patterns, as well as dependency-driven trace-based simulation (Netrace), are implemented and will be demonstrated

Routage adaptatif pour MPSoC résistant aux défaillances de noeuds et de liens

National audienc